By Ming-Dou Ker
The publication all semiconductor equipment engineers needs to learn to achieve a realistic consider for latchup-induced failure to supply lower-cost and higher-density chips.
Transient-Induced Latchup in CMOS built-in Circuits equips the training engineer with all of the instruments had to tackle this common challenge whereas turning into more adept at IC structure. Ker and Hsu introduce the phenomenon and uncomplicated actual mechanism of latchup, explaining the severe matters that experience resurfaced for CMOS applied sciences. as soon as readers can achieve an realizing of the normal practices for TLU, Ker and Hsu speak about the actual mechanism of TLU below a system-level ESD try out, whereas introducing a good component-level TLU dimension setup. The authors then current experimental methodologies to extract secure and area-efficient compact format principles for latchup prevention, together with structure principles for I/O cells, inner circuits, and among I/O and inner circuits. The booklet concludes with an appendix giving a realistic instance of extracting structure ideas and directions for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process.
- Presents actual instances and recommendations that happen in advertisement CMOS IC chips
- Equips engineers with the talents to preserve chip format sector and reduce time-to-market
- Written through specialists with real-world event in circuit layout and failure analysis
- Distilled from various classes taught by way of the authors in IC layout homes worldwide
- The basically publication to introduce TLU lower than system-level ESD and EFT tests
This ebook is key for practising engineers considering IC layout, IC layout administration, approach and alertness layout, reliability, and failure research. Undergraduate and postgraduate scholars, focusing on CMOS circuit layout and format, will locate this booklet to be a necessary advent to real-world difficulties and a key reference in the course of the process their careers.
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